Impedance measurement on power lines

Good question — this is a real and underappreciated board-test risk. Let me address it directly.

Your concern is well-founded. Many precision multimeters in resistance mode apply an open-circuit test voltage that can be significantly higher than the rated operating voltage of sensitive rails. A 9 V open-circuit voltage on a 0.9 V FPGA core rail or a 0.75 V DDR3 Vtt rail is well above the absolute maximum ratings for those supplies, and even a brief transient at that level can cause damage or latent degradation — particularly on fine-geometry FPGA core logic and DDR3 termination circuits.

Altera's documentation reinforces the sensitivity of these rails. For example:

• For Agilex 5, the guidance is explicit: to prevent damage, do not drive VSIGP and VSIGN pins until the VCCADC power rail has reached 1.62 V Power Management User Guide Agilex™ 5 FPGAs and SoCs — illustrating how seriously sequencing and voltage thresholds are treated even for analog measurement pins.


• Power supply noise is a key parameter for sensitive rails such as transceiver voltage rails, directly impacting jitter and bit error rate (BER) AN 721: Creating an FPGA Power Tree — so even sub-damage-level transients on sensitive rails matter.

Regarding your shunt resistor workaround: your 1 kΩ shunt approach is sound engineering practice and is exactly the right mitigation. By placing a 1 kΩ resistor across the probes, you clamp the open-circuit voltage to a safe level (the multimeter's short-circuit current through 1 kΩ stays in the µA range, producing millivolts rather than volts). The tradeoff — that your measurable range is now 0–1 kΩ — is entirely manageable for board-level power rail impedance checks, where you are looking for gross faults (shorts, opens, missing decoupling) rather than precision impedance values.

A few additional recommendations consistent with good PDN practice:

• If the FPGA shares a power rail with another device, reducing PDN parasitic inductance and increasing isolation between the FPGA and any noise source reduces risk — and you must perform a transfer impedance analysis to clearly identify any noise interference risk. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide Your multimeter test voltage is effectively an injected noise source on the rail, so the same principle applies.


• For DDR3 Vtt specifically: when calculating the tolerance for DDR3 Vtt supplies using SSTL15, it is with respect to VCCIO, and you should also take the VCCIO tolerance into the calculation — giving a tight window of approximately ±50 mV across min/max conditions. How do I calculate the tolerance on the Vtt supply for DDR3? A 9 V test stimulus is orders of magnitude outside this window.


• Some engineers also use a low-voltage LCR meter (set to a 100 mV or 500 mV AC stimulus) for PDN impedance spot-checks — this keeps the stimulus well within safe operating voltage for all rails while still giving meaningful impedance data.

In summary: continue with your 1 kΩ shunt method. It is a practical, safe, and well-reasoned approach. The alternative of using a meter with a selectable low-voltage test mode (some Keysight/Fluke bench meters allow this) or an LCR meter with a low AC stimulus is also worth considering for production test environments.