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Altera_Forum's avatar
Altera_Forum
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16 years ago

Ignoring timing violations

Hello everyone, I need help in setting some timing constraints. I have high frequency data lines which are constrained with 275MHz clock. Also, I have another input signals which work with the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Is maybe the "Cut Timing Path" setting appropriate in this case ?