Ignoring timing violations

Question

Hello everyone,

I need help in setting some timing constraints. I have high frequency data lines which are constrained with 275MHz clock. Also, I have another input signals which work with the same frequency but are not crucial for the design and the constraints can be violated. How shall I set the fitter to ignore optimization of these lines and classic timing analyzer to disable warnings ?

Best Regards

Joel

altera_forum · Answer

Is maybe the "Cut Timing Path" setting appropriate in this case ?

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Ignoring timing violations

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