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Altera_Forum's avatar
Altera_Forum
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13 years ago

If generate statement in vhdl for enabling and disabling hardware

I want to enable or disable logic using en_logic from external environment en_logic is defined as a std_logic input signal from external environment not_gen_logic : if (en_logic = '0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Generate statements are used to create different static implementations.

What you are really after is using en_logic as a multiplexer control. 


in(1 to 4) <= rx_inp(1 to 4) when (en_logic = '0') else rx_inp(5 to 8);
Cheers,

Dave