if condition for modules? (verilog question)

Hi ayhoung,

verilog does not allow to instanciate a module (here touch_panel) based on the value of a signal (here iSW[1]).

--- Quote Start ---

always @ (posedge iCLK_50)

begin

if(iSW[1])

begin

touch_panel tp1 ( //<---module declaration

.iCLK(ltm_nclk),

--- Quote End ---

In real hardware it would mean that depending a logic input signal on a printed circuit board you would magically add (or remove) an integrated circuit component.

You can however use a multiplexer to select these signals that you want to enter to another module.

e.g.

 
if (iSW) begin
  lcd_R = camera1_buffer_R;
  lcd_G = camera1_buffer_G;
  lcd_B = camera1_buffer_B;
end else begin
  lcd_R = camera2_buffer_R;
  lcd_G = camera2_buffer_G;
  lcd_B = camera2_buffer_B;
end

When working with video signals you should of course be careful that the signals you are connecting are compatible in format and timing. Otherwise this will not work.

Hope this helps...