I2S receiver clocked on "high-transition-time" clock

I am using a cyclone IV device to read data from an AD (I2S bus). the receiving logic is clocked on the I2S clock.

the problem is that the "receiver" module does not produce any signal-activity at all when clocked from the AD (seen with signaltap). when i generate a clock-signal from the FPGA instead, and wire it to the receiver input clockpin - it behaves as expected.

i think this might be a timingproblem caused by the clocksignal has a very high input transition time. i measured it with a scope to be about 20 ns (90-10 and 10-90). Timequest thinks it is 2,6 ns.

am i right that this could be the root of my problem - and can i adjust this in quartus or timequest to reflect what i am measuring?