Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI2S receiver clocked on "high-transition-time" clock
I am using a cyclone IV device to read data from an AD (I2S bus). the receiving logic is clocked on the I2S clock. the problem is that the "receiver" module does not produce any signal-activity...
Altera_Forum
Honored Contributor
15 years agoSOLVED.
Reduced transition-time on driver side.