I2C on EPM570M100

Not according to the specification. Both SCL edges are significant in the slave logic. I don't have a HDL I2C code at hand, but usual uP software implementations have a delay after changing either SDA or SCL. This would be the basic method for a HDL implementation (usually based on a fast system clock): Have a state machine and a delay timer.

A very simple (but typically undocumented and somewhat cryptic Verilog I2C master code) can be found with the Terasic DE2 demonstrations. Also opencores.org has some I2C projects, but possibly more complex than necessary for your application.