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Altera_Forum
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17 years ago

I2C on EPM570M100

Hi all, I am trying to implement the I2C protocol (master side) on an EPM570 CPLD. I am new to VHDL so I am having trouble finding the errors of my code. Basically the code is working, I can s...
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Altera_Forum
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17 years ago

I see in Quartus simulator, that SDA is changed simultaneously with rising SCL edge, which is not complying to the I2C specification. I see, that SDA is driven in push-pull mode. This may possibly work, but do you have also an SDA pullup resistor as required at least for data reception.

Generating a correct I2C timing requires more than two clock phases per bit. It may be, that the AD7151 tolerates some deviations from I2C specification, but would expect, that they tested the device with an I2C master following the standard, e. g. a uP with I2C interface.