I2C on EPM570M100

What you will need to think about is the clock edge that is latching each data bit into the FPGA.

I am assuming your external device will drive data out on a rising edge of the clock. If you then latch read data internal to the FPGA on the same edge then depending on your FPGA timing/external interface timing you may or may not latch the correct data.

For example if the period from clock rising to you latching data inside the FPGA is less than the time taken from Clock rising to the External part driving data + the transmission delay back to the FPGA then the data latched will be incorrect.

I am not an I2C expert so am not 100% sure that the the rd/wr data is driven on the rising edge but it is worth taking a look at. Look at the timing diagrams of your analog devices part and try and work out what will happen

Hope this helps