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HT4's avatar
HT4
Icon for New Contributor rankNew Contributor
7 years ago

I want to use PS programming through CPLD and a flash. I have some uncertainties for programming and circuit design

I am using Cyclone IV GX FPGA Does the flash should have specific feature to be able to use as memory for different configuration file? or just meeting the minimum required memory is the only condi...
ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hello HT, 1. Usually for PS configuration, we recommend to user to follow the supported flash memory devices for FPL IP. You may refer to the supported flash memory devices for PFL IP in the following link (Table 1 and 2 on page 4): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf#page=4 2. Yes, you can program more than one configuration file into the flash. Quartus can handle it properly. 3. Basically, you need to have Parallel Flash Loader (PFL) IP to control configuration from the flash device. And the fpga_pgm[ ] pin signal is used to determine the page for the configuration. You may refer to the information the PFL IP core input and output signals in the Table 17 (on page 41) https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf#page=41 4. You may refer to the PFL IP user guide and Cyclone IV pin connection guide during circuit design. PFL = https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf Pin connection = https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf Thanks.
  • HT4's avatar
    HT4
    Icon for New Contributor rankNew Contributor
    7 years ago

    I want to use MX25L12833F that is supported by Intel but the concept for paging in their datasheet with what Intel talks in the datasheet looks diffeernt to me.

    can you confirm if it supports multiple configuration or not?

    Thanks!