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Altera_Forum
Honored Contributor
17 years agoI want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C
I have a DK-DSP-3C120N KIT,the NIOS II clock can not exceed 100mhz.The highest speed of NIOS II /f is now just 100mhz.The C program always dead when the clock exceed 100mhz.I want to working at least...
Altera_Forum
Honored Contributor
16 years agoAfter running the Read SDC, I noticed that somehow it creates the altera_reserved_clk with the same name, altera_reserved_clk, This can be seen by Running "Report Clocks" on the Diagnostic section.
There fore I uncoment the generation of the clock from the template, and change the references from tck to altera_reserved_tck. # create_clock -name tck -period __period [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port set_input_delay -clock altera_reserved_tck -clock_fall 20 [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock altera_reserved_tck -clock_fall 20 [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock altera_reserved_tck -clock_fall 20 [get_ports altera_reserved_tdo] This is at least constraining the altera paths, however I am not tottally sure if this is correctly contrained, I would like to know if it is correct. I hope someone find this usefull. Thankyou