I want to design FIR and IIR Filters...

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At 500 samples per second your FPGA has many many clock cycles to perform calculations. You can use a single multiplier and RAM and implement the FIR.

The IIR should be able to be implemented with 2 (Butterworth) or 5 multipliers per second-order-section.

You should perform a bit accurate simulation using a FIR/IIR design tool to determine the filter parameters.

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thanks for the advices

I think that I need to have my filter design completely ready first, I'm using Matlab for this

I was afraid that my desing wouldn't fit in my cyclone II , I need to determinate all parameters first and chose an implementation