I want to design FIR and IIR Filters...

--- Quote Start ---

which FPGA is the best?

Cyclone

Arria

or

Stratix

--- Quote End ---

It depends on what 'best' means to you?

They can all implement FIR and IIR filters.

What kind of implementation were you planning on? Are the coefficients optimized to be simple right-shifts, or are full multipliers required?

If you are using multipliers, how many bits do your multipliers require?

What is the sample rate of your filter? How many coefficients do the filters have?

If you can answer these questions for yourself, then you can look at the data sheets and see that the higher-end devices have better multipliers (more bits) and what density you need to meet your bandwidth and multiplication rate requirements.

Cheers,

Dave

sorry I didn't mention the specifications

for FIR

low-pass filter, order 55, with a cutoff at 10 hz, 500 samples/second

IIR

order 1, attenuation at 22 db

the thing is that i don't know which implementation is the best for use in order to save resources

until now I only had thinking in use flip-flops, multipliers and adders, but I think that this needs a lot of LEs

also I haven't decided the number of bits for the coefficients

I have a cyclone II ep2c8q208c7 (8300 LEs, 18 18x18-bit multipliers) and I have already use around 15% of the LEs

there is another way for implement the filter?

I'm kind of lost, thanks for the advices

--- Quote Start ---

for FIR

low-pass filter, order 55, with a cutoff at 10 hz, 500 samples/second

IIR

order 1, attenuation at 22 db

the thing is that i don't know which implementation is the best for use in order to save resources

until now I only had thinking in use flip-flops, multipliers and adders, but I think that this needs a lot of LEs

also I haven't decided the number of bits for the coefficients

I have a cyclone II ep2c8q208c7 (8300 LEs, 18 18x18-bit multipliers) and I have already use around 15% of the LEs

there is another way for implement the filter?

--- Quote End ---

There are many different ways to implement filters.

At 500 samples per second your FPGA has many many clock cycles to perform calculations. You can use a single multiplier and RAM and implement the FIR.

The IIR should be able to be implemented with 2 (Butterworth) or 5 multipliers per second-order-section.

You should perform a bit accurate simulation using a FIR/IIR design tool to determine the filter parameters.

Cheers,

Dave

--- Quote Start ---

for FIR

low-pass filter, order 55, with a cutoff at 10 hz, 500 samples/second

--- Quote End ---

As Dave explained, a low speed filter like this can be easily implemented serially. A different point is, that the filter specification doesn't make much sense for a high-order FIR filter. The problem is, that "order 55" doesn't represent more than a single cycle at the 10 Hz cut-off. This implies, that the filter coefficients don't give much freedom of tuning the filter shape around the cut-off frequency, which would usually be the purpose of a FIR filter. I expect, that a low order IIR filter gives similar performance in this case. You should try yourself with a filter software tool.

Any digital filter's cutoff is relative only (e.g. to Nyquist or to Fs).

cutoff = 10/500 = .02

A filter that fulfills this cutoff does not care about actual frequency of signal.

Never heard of that cycle explanation??

--- Quote Start ---

At 500 samples per second your FPGA has many many clock cycles to perform calculations. You can use a single multiplier and RAM and implement the FIR.

The IIR should be able to be implemented with 2 (Butterworth) or 5 multipliers per second-order-section.

You should perform a bit accurate simulation using a FIR/IIR design tool to determine the filter parameters.

--- Quote End ---

thanks for the advices

I think that I need to have my filter design completely ready first, I'm using Matlab for this

I was afraid that my desing wouldn't fit in my cyclone II , I need to determinate all parameters first and chose an implementation

--- Quote Start ---

A different point is, that the filter specification doesn't make much sense for a high-order FIR filter. The problem is, that "order 55" doesn't represent more than a single cycle at the 10 Hz cut-off. This implies, that the filter coefficients don't give much freedom of tuning the filter shape around the cut-off frequency, which would usually be the purpose of a FIR filter. I expect, that a low order IIR filter gives similar performance in this case. You should try yourself with a filter software tool.

--- Quote End ---

I think I understand your point, but not completely, I´m starting whith FIR and IIR filters so I'm going to check over my desing

--- Quote Start ---

Never heard of that cycle explanation??

--- Quote End ---

neither do I, I will review more about filters

--- Quote Start ---

I will review more about filters

--- Quote End ---

Read these;

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

There are plenty of cross-references in there for you to look at too.

Cheers,

Dave

--- Quote Start ---

Never heard of that cycle explanation??

--- Quote End ---

Consider it as my personal rule of thumb "where not to use FIR filters". I didn't say, that a filter with fc = 0.02 and 55 taps isn't feasible. I claim, that it's ability to achieve a specified frequency response will be very limited and thus an IIR filter will better achieve a typical low-pass characteristic.

If you doubt, that there is a relation between filter performance and relative filter length, you should compare the results of fc 0.01, 0.02 and 0.1 low-passes with L=55.

FIR filter design literature gives more exact expressions for the required filter length depending on stop band attenuation and pass and stopp band frequency. Typical relative lengths are considerable larger than L > 1/fc.

The FIR design chapter of U.Meyer-Baese digital signal processing with fpga gives a brief overview of popular design methods.