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zlan01's avatar
zlan01
Icon for New Contributor rankNew Contributor
6 years ago

I do not have the input reset signal from the outside of the Altera FPGA,and want to generate reset internally;can I do like below ?

if the pll is used to generate 4 output clock, and the input clock is 20Mhz,the output is 400Mhz, 25Mhz, 50Mhz ,30Mhz ,I wil implement 4 counters drived by the 4 output clock, and can I use the 4 conters to generate the 4 resets according to the 4 differerent output clocks?

and do the 4 resets have the features of asynchronously asserting and synchronously deasserting in their clock domain?

if I can do like above, can the code below work ?out_clk1 is the first output of the pll.

always@(posedge out_clk1)

begin

if(counter1 < 10'd505)

counter1 <= counter1 + 10'd1;

end

assign cnt_reset_n1 =( counter1 == 10'd500 ) ? 1'b0:1'b1;

will cnt_reset_n1 become low just for one out_clk1 ?

will cnt_reset_n1 has the feature of asynchronously asserting and synchronously deasserting according to the out_clk1 ?

1 Reply

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    here is my thought on the RTL above ,

    Actually this RTL will generate the reset asseration and and de-asseration of the reset signal for one clokc ; There are two things i am concern about are below

    i) Inital state of the counter, In the RTL you must define the intial state of the counter which has to happen in reset stage. My question to you here ..Do you have any signal which can be used as the reset signal input for the design ? or anothe idea cna it use one clock as define the state of the counter and next consective clk starts count ?

    ii) When you say Reset to the external from the FPGA , then i wont be able to tell it is syn or asyn reset becase reset domain depends on where it is feeded to not it is generated right ?

    Thank you ,

    Regards,

    Sree

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