I do not have the input reset signal from the outside of the Altera FPGA,and want to generate reset internally;can I do like below ?

here is my thought on the RTL above ,

Actually this RTL will generate the reset asseration and and de-asseration of the reset signal for one clokc ; There are two things i am concern about are below

i) Inital state of the counter, In the RTL you must define the intial state of the counter which has to happen in reset stage. My question to you here ..Do you have any signal which can be used as the reset signal input for the design ? or anothe idea cna it use one clock as define the state of the counter and next consective clk starts count ?

ii) When you say Reset to the external from the FPGA , then i wont be able to tell it is syn or asyn reset becase reset domain depends on where it is feeded to not it is generated right ?

Thank you ,

Regards,

Sree