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Ok i got it working. It was something i had no idea would make a difference but thought i'd try it. I hope you might be able to explain or help me understand why this makes a difference
I added what a few other designs i've seen call a pipeline buffer- code below
From looking at this, it just seems like the audio samples are being synced upto the system clock edge but i dont understand why that is necessary.
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Nor will anyone else likely be able to figure out why is was necessary since you haven't posted your entire design (both the 'working' and the 'not working'). Synchronizing signals to a clock is necessary when asynchronous signals or signals from a different clock domain are used with synchronous logic, but the original code you posted has no clock so that wouldn't be the case...unless you haven't posted something that is relevant to the design. As an example, it is not even clear how your samples have morphed into a 'left' and a 'right'.
Kevin
Honored Contributor
