I cant work this out!

Ok i got it working. It was something i had no idea would make a difference but thought i'd try it. I hope you might be able to explain or help me understand why this makes a difference

I added what a few other designs i've seen call a pipeline buffer- code below

From looking at this, it just seems like the audio samples are being synced upto the system clock edge but i dont understand why that is necessary.

library IEEE;
use IEEE.std_logic_1164.all;
entity pipeline_buffer is
	port (
		
		clk: in std_logic;
		lrclk: in std_logic;
		reset: in std_logic;
				
		-- data
		sample_in_left: in std_logic_vector(15 downto 0);
		sample_out_left: out std_logic_vector(15 downto 0);
		sample_in_right: in std_logic_vector(15 downto 0);
		sample_out_right: out std_logic_vector(15 downto 0)
		
	);
end entity pipeline_buffer;
architecture beh of pipeline_buffer is
	signal last_lrclk: std_logic;
begin
	process (clk, reset)
	begin
		if (reset='0') then
			sample_out_right <= (others => '0');
			sample_out_left <= (others => '0');
		elsif rising_edge(clk) then
			sample_out_right <= sample_in_right;
			sample_out_left <= sample_in_left;
		end if;
	end process;
end architecture beh;