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I meant simply to look in the timing report to see if Quartus is reporting a Tpd path from every input pin to every output pin. It should since your design as posted should result in a totally combinatorial logic path. The thought is that somehow things didn't get connected in a higher up level which if they didn't would result in some pins not having such a path. However, since you've used the netlist viewer on the post map to verify that there are indeed all of the logic paths there is no need to look for a timing path.
About the only thing left is that the switches are not hooked up on the board to the pins that you are specifying in the FPGA design. Verify with a scope or meter that when you change a particular switch setting that the pin in question really does toggle and go to the expected voltage level.
Kevin Jennings
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The switches are definitely connected, i used them to control the on board LEDS.
I've tried so many different things here!
The only other thing i can think of is that maybe its some kind of syntax problem for example do i need to specify i want to use the binary value of 'SW' and multiply this. I'm guessing this is assumed though.
Honored Contributor
