I cant work this out!

Thanks for the replies. Your right, i messed the copy/pasting up. However, my problem still stands.

As soon as i change the multiply by SW to a binary value eg ("0000000000111111") then the volume changes as expected.

Both version compile fine. All i want to do is have the the switches represent that 16 bit binary multiplying value.

I've done things more complicated than this but for some reason i just cant see whats going wrong here. There is no audio output suggesting all the samples are being multiplied by zeros. The switches are connected on the top level in block diagram format. SW[15..0]

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity volume is
	port (
				
		-- data
		sample_in: in std_logic_vector(15 downto 0); --zero is msb
		sample_out: out std_logic_vector(15 downto 0);
		
		-- params
		SW: in std_logic_vector(15 downto 0)
	);
end entity volume;
architecture beh of volume is
	signal signal_unnormalized: std_logic_vector(31 downto 0);
begin
	signal_unnormalized <= sample_in * SW;
	
	sample_out <= signal_unnormalized(31) & signal_unnormalized(22 downto 8);
end architecture beh;