I cant work this out!

Couple of points:

1. You didn't do a good job of copy/pasting because you have a signal called 'sample_reg' but you have an assignment that cannot compile:

sample_out<=sample reg; -- Note the space between 'sample' and 'reg'

2. The output of the entity sample_out even if it was connected to 'sample_reg' as you no doubt intended, still has a problem in that you never assigned anything to 'sample_reg' so 'sample_out' will get set to all zeros since sample_reg is unassigned.

3. You have two assignments to sample_out. This would never make it through any synthesis tool because it would mean that there are two drivers for sample_out and the tool would end with an error. Simulation would show that there are two drivers after you scratch your head for a few minutes debugging. However, if you use std_ulogic_vector rather than std_logic_vector (similarly, use std_ulogic rather than std_logic for bits) than the simulator will flag the error during a compile as well...without having to debug anything.

Since you're a beginner, I would suggest learning how to use a simulator. Once you're even mildly proficient, you will be far more productive debugging problems in a simulation environment...much more so than debugging hardware or asking on a forum (not a criticism, just a suggestion).

For your current problem, you can ignore Tricky's question about why you are not using a clock for a synchronous design. Your design as posted has no need for a clock, or a process. It's fine except for the items I noted above (assuming that you did get the pin numbering correct as Tricky suggested that you verify, which you say you did).

Kevin Jennings