Forum Discussion
Altera_Forum
Honored Contributor
8 years agoQSYS makes a copy of all the hdl files when you generate the hdl, so you are right that each time you modify your HDL files you need to regenerate the QSYS system before compiling the project again. Or you edit the copies, but you risk getting them overwritten the next time you click generate.
There is no "back-up" of the project for signal tap, as long as you make sure that the QSYS system has been regenerated, this is what will be in the FPGA and what you will see in signaltap. What you can see is the waves from the previous run, if you saved a signaltap file with data. But as soon as you click "run analysis", it will be overwritten with new data. After you compiled the project you can use the RTL viewer to check that your code modifications have been implemented by Quartus. (and generally the RTL viewer is great when you need to check that Quartus understood what you meant in your code).