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Altera_Forum's avatar
Altera_Forum
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8 years ago

I can't modify a file in quartus after generated the QSYS system? Please Help.

I'm making a flash controller in FPGA. I wrote the principal controller code, and another file that works like a test bench (a counter that generates the write and read instructions with datas) I nam...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I just realize the QSYS must be not the problem. If I modify a file originating the custom logic in qsys, I just have to generate the HDL from QSYS again and consequently the file inside the QSYS .qip keep the changes.

The problem seems to be in the Logic Tap II analyzer. I can only see the wave belonging to the original file which I first created the .stp file, but now, no matter if I create a new STP file and delete the old STP file, when I run the Signal Tap and trigger, it still show me the old version of the verilog code. So, I'm guessing the problem is that Signal Tap II is addressing to a kind of internal "backup" of the original file (which technically does not exist anymore because I made the changes) but it does not show me the modified file wave as I wish.

Ommit the message in the attached image, that's not the problem anymore, problem arise only in the signal tap II, because it does not show me the modified wave.

Any ideas?