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YAror's avatar
YAror
Icon for New Contributor rankNew Contributor
6 years ago

I am not able to detect Electrical Idle signal in simulation while using Intel® Arria® 10 Transceiver PHY How to detect it ?

I am using Intel® Arria® 10 Transceiver PHY in a project which is later used for a non pci based protcocol, I am driving Tx_pma_elecidle signal at the tx pma side

but not able to detect rx_elecidle signal at the rx side in simulation (using Modelsim Altera) , even when i force tx_pma eelecidle the serial tx bit

is getting to hold a 'Z' value which seems to be okay ,so idea is within the RX circuit ,it will detect this 'Z' as rx_elecidle signal ,not sure whether there is a provision in simulation to detect it or not.

elecidle inference is set to zero ,and cdr is lock to reference ,

I have also attached a screenshot of the simulation in which tx and rx serial bits re connected via wire.

Please give some suggestions to move this up in simulation ..

3 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    As I understand it, you have some inquiries related to the RX electrical idle. To ensure we are on the same page, just would like to check with you on the following:

    1. When you are referring to rx_elecidle, is it that you are referring to "pipe_rx_elecidle" output signal?

    2. Just wonder if you are configuring the Native PHY to PCIe mode? For your information, the pipe_rx_elecidle is used only for PCIe configuration. It is not used for non-PCIe mode.

    3. Please feel free to share with me your Native PHY .qsys file so that I can have a better understanding of your configuration.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

  • YAror's avatar
    YAror
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi ,

    Thanks for replying.

    Please find my answers below.

    1. When you are referring to rx_elecidle, is it that you are referring to "pipe_rx_elecidle" output signal?

    Answer :Yes , I am referring to pipe_rx_elecidle.

    2. Just wonder if you are configuring the Native PHY to PCIe mode? For your information, the pipe_rx_elecidle is used only for PCIe configuration. It is not used for non-PCIe mode.

    Answer :Agreed, My understanding to the config of the IP is that for PCIe protocols, there are particularly PIPE interfaces present , but there is an optional pcie signals also present that can be used with other protocols as well , by inferring these signals by the user, and pipe_rx_elecidle is one of them , so expectation is pipe_rx_elecidle will be one if tx_pma_force_elcidle is set to high ,

    So in case this understanding is not correct , could you please help me with , how to detect elecidle signal in simulation for a non pcie based protocol like USB 3.0.

    3. Please feel free to share with me your Native PHY .qsys file so that I can have a better understanding of your configuration.

    Answer : I am using Quartus prime 19.3, I have below attached(.ip) file to show you the configuration for the IP , I hope it will suffice for what you asked.

    Please feel free to revert with more questions in case of any doubts

    Regards

    -Y.Arora

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Sorry for the delay. Thanks for your clarification. For your information, pipe_rx_elecidle only work for PCIe configuration. For non-PCIe mode, the signal would not work. In other words, the pipe_rx_elecidle will not assert in non-PCIe mode when the tx_pma_force_elecidle is asserted. Sorry for the inconvenience.

    Regarding your inquiry on how to detect elecidle signal in simulation for non PCIe mode ie USB 3.0, sorry as I do not have much insight into this and could not further comment on this. If you would like to further engage our Design Service partner for USB 3 related IP or design in A10 devices, you may try further look into the following link to see if it helpful. Note that there will be charges.

    https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/system-level-solutions--inc-/ip/embedded-usb-3-1-gen-2-device-controller--eusb31sf-.html

    You may also visit the following and search for "usb" to find other USB related partners:

    https://www.intel.com/content/www/us/en/programmable/solutions/partners/design-solutions-network/ip-result.html?

    Please let me know if there is any concern. Thank you.