I am not able to detect Electrical Idle signal in simulation while using Intel® Arria® 10 Transceiver PHY How to detect it ?

Hi ,

Thanks for replying.

Please find my answers below.

1. When you are referring to rx_elecidle, is it that you are referring to "pipe_rx_elecidle" output signal?

Answer :Yes , I am referring to pipe_rx_elecidle.

2. Just wonder if you are configuring the Native PHY to PCIe mode? For your information, the pipe_rx_elecidle is used only for PCIe configuration. It is not used for non-PCIe mode.

Answer :Agreed, My understanding to the config of the IP is that for PCIe protocols, there are particularly PIPE interfaces present , but there is an optional pcie signals also present that can be used with other protocols as well , by inferring these signals by the user, and pipe_rx_elecidle is one of them , so expectation is pipe_rx_elecidle will be one if tx_pma_force_elcidle is set to high ,

So in case this understanding is not correct , could you please help me with , how to detect elecidle signal in simulation for a non pcie based protocol like USB 3.0.

3. Please feel free to share with me your Native PHY .qsys file so that I can have a better understanding of your configuration.

Answer : I am using Quartus prime 19.3, I have below attached(.ip) file to show you the configuration for the IP , I hope it will suffice for what you asked.

Please feel free to revert with more questions in case of any doubts

Regards

-Y.Arora