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Physical synthesis, as you mention, may fix the problem, though it will greatly increase compile time. If you must use a global, you may want to see if you should be using a different clock control block. That insertion delay (the time to get to the clock control block) is pretty long (4.1 ns), so you should check to see if the Fitter selected the closest clock control block for getting the reset on the global clock.
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It is as close as it can be. The theory is that the fitter is trying to compensate for hold on the reset for some of the registers (because 4.1ns is rather large when you're only going from the register adjacent to the CLKCTRL!) , so is inserting extra routing delay to fix it, and breaking the recovery for everything else. So Im adding a fitter only constraint to relax hold timing so that these will then fail hold or removal timing so I can isolate and fix them.
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