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Ok - Ive found this interesting page:
http://quartushelp.altera.com/15.0/mergedprojects/logicops/logicops/def_physical_synthesis_asynchronous_signal_pipelining.htm Anyone know if I can determine if a signal is dertermined to be "critical"?
The Pipeline asynchronous signal option is enabled in project settings - and it seems to fit with my problem exactly.
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I am no fan of using tool to do such job and I would rather do the pipeline myself as it is straightforward.
Remember the modules distant in a chain can't get all released at reset in same clock period as front modules due to massive delay.
Unlike clock and data which delay together through the chain. If your design units at rear of chain do not have feedback and will work well after reset release then it is safe to pipeline the reset. Otherwise you shouldn't pipeline and your design will fail timing.
Honored Contributor
