Huge numbers of recovery failures - even though reset is on Global Clock Net

Global resetting everything was the design choice when the project started several years ago. Now w're on a global (rather than local) resets we picked out many cases where synchronous enables were infered from the reset. This is the design choice that was taken to must stick with it (I wouldnt do this now... but others might think differently..), as almost all of the code does this.

I want to avoid false paths just in case something gets borked when coming out reset (its highly unlikely, but I want to avoid it unless necessary, though Im pretty sure it would be safe). At the moment, the reset is synchronised using a counter (16 bit) and a 2nd register when the counter rolls over. This should smooth out any bounces from the PLL locked signal thats used as one of the inputs. Other reset inputs are HWreset pin and sw reset. Theres no hand shaking.

It was suggested we put a shift register as the output of the reset block. This, combined with possible reset pipelining options might be useful - ill give it a go (6 hr build - slow progress)