HSMC Pinout on Stratix II

The HSMC connector pin mapping to FPGA pins is included in the board manual, may be it's also included in example designs. From the pin mapping, you identify, that e. g. hsma_rx_n and _p pins are GXB pins, while hsma_d_rx_n and _p are LVDS-pins, that can be used as single ended I/O also. You can also identify, that hsma_clk_out0 is a PLL11 output intended as single-ended clock, while hsma_clk_out_n and _p are LVDS outputs but not dedicated clock outputs. So hsma_clk_out0 should be used, if a dedicated clock output is required, but the 100 MHz clock present at the port can be routed to any I/O pin with reduced timing accuracy.