HSMC Pinout on Stratix II

The HSMC signal names sounds almost self-explananatory to me, also without knowing a specification. You have single-ended data lines and line pairs intended for differential signals. The latter are connected to Stratix I/O pins capable of LVDS differential IO, Rx or Tx respectively. Other lines are intended as clocks, connected to dedicated clock FPGA pins.

As with all designs, the actual usage of the signals depends on your design. E.g., if you want to use LVDS Tx from FPGA, you are restricted to dedicated FPGA pins, otherwise you can use these pins as you like. Then the p and n designators wouldn't mean a thing.