Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

"HREAD" is used but not declared"-Read text image data Error

Hi,

I try simulate testbench code for read text image data (project example). I have includes all the package required (textio), but when I compile it I get this error:

"Error (10482): VHDL error at INPIMAGE.VHD(150): object "HREAD" is used but not declared".

Why this error occur? :confused: I just follow the same code as example. Need helps from anyone expert with textio library. Below is the pieces of the code.

library WORK;

use WORK.MDCT_PKG.all;

use WORK.MDCTTB_PKG.all;

use WORK.RNG.all;

entity INPIMAGE is

port (

clk : in STD_LOGIC;

odv1 : in STD_LOGIC;

dcto1 : in STD_LOGIC_VECTOR(OP_W-1 downto 0);

odv : in STD_LOGIC;

dcto : in STD_LOGIC_VECTOR(COE_W-1 downto 0);

rst : out STD_LOGIC;

imageo : out STD_LOGIC_VECTOR(IP_W-1 downto 0);

dv : out STD_LOGIC;

testend : out BOOLEAN

);

end INPIMAGE;

architecture SIM of INPIMAGE is

constant PERIOD : TIME := 1 us /(CLK_FREQ_C);

signal rst_s : STD_LOGIC;

signal test_inp : INTEGER;

signal test_stim : INTEGER;

signal test_out : INTEGER;

signal xcon_s : INTEGER;

signal ycon_s : INTEGER;

signal error_dct_matrix_s : I_MATRIX_TYPE;

signal error_dcto1_matrix_s : I_MATRIX_TYPE;

signal imageo_s : STD_LOGIC_VECTOR(IP_W-1 downto 0);

signal dv_s : STD_LOGIC;

begin

rst <= rst_s after HOLD_TIME;

imageo <= imageo_s after HOLD_TIME;

dv <= dv_s after HOLD_TIME;

--------------------------

-- input image stimuli

--------------------------

INPIMAGE_PROC: process

variable i : INTEGER := 0;

variable j : INTEGER := 0;

variable INSERT_DELAYS : BOOLEAN := FALSE;

variable unf: Uniform := InitUniform(7, 0.0, 2.0);

variable rnd: real := 0.0;

variable xi : INTEGER := 0;

-------------------------------------

-- wait for defined number of clock cycles

-------------------------------------

procedure waitposedge(clocks : in INTEGER) is

begin

for i in 1 to clocks loop

wait until clk='1' and clk'event;

end loop;

end waitposedge;

-------------------------------------

-- wait on clock rising edge

-------------------------------------

procedure waitposedge is

begin

wait until clk='1' and clk'event;

end waitposedge;

--------------------------------------

-- read text image data

--------------------------------------

procedure read_image is

file infile : TEXT open read_mode is FILEIN_NAME_C;

variable inline : LINE;

variable tmp_int : INTEGER := 0;

variable y_size : INTEGER := 0;

variable x_size : INTEGER := 0;

variable x_blocks8 : INTEGER := 0;

variable y_blocks8 : INTEGER := 0;

variable matrix : I_MATRIX_TYPE;

variable x_blk_cnt : INTEGER := 0;

variable y_blk_cnt : INTEGER := 0;

variable n_lines_arr : N_LINES_TYPE;

variable line_n : INTEGER := 0;

variable pix_n : INTEGER := 0;

variable x_n : INTEGER := 0;

variable y_n : INTEGER := 0;

begin

READLINE(infile,inline);

READ(inline,y_size);

READLINE(infile,inline);

READ(inline,x_size);

y_blocks8 := y_size / N;

x_blocks8 := x_size / N;

assert MAX_IMAGE_SIZE_X > x_size

report "E02: Input image x size exceeds maximum value!"

severity Failure;

if y_size rem N > 0 then

assert false

report "E03: Image height dimension is not multiply of N!"

severity Failure;

end if;

if x_size rem N > 0 then

assert false

report "E03: Image width dimension is not multiply of N!"

severity Failure;

end if;

for y_blk_cnt in 0 to y_blocks8-1 loop

-- read N input lines and store them to buffer

for y_n in 0 to N-1 loop

READLINE(infile,inline);

HREAD(inline,n_lines_arr(y_n)(0 to x_size*IP_W-1));

end loop;

y_n := 0;

Any helps greatly appreciated. Thank you

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    where is the declarataion of n_lines_type?

    If its an array of std_logic_vector, you need to include the ieee.std_logic_textio package.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    where is the declarataion of n_lines_type?

    If its an array of std_logic_vector, you need to include the ieee.std_logic_textio package.

    --- Quote End ---

    I just copy & paste the testbench code from the project example. I not sure the declaration of n_lines_type is missing or not needed. But, the ieee.std_logic_textio package already included in the code,when the error occurred. What I missing?:confused: Thanks for your concern Tricky!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Yes, you can only run the testbench in modelsim. Textio is not appropriate for synthesys, hence why you cannot compile in Quartus.

    The error you are getting is a type missmatch, you probably need to convert them using the to_signed(int, size) function.

    If you are unfamiliar with this, and textio, I suggest you read some VHDL tutorials, as these are very basic parts of VHDL.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Yes, you can only run the testbench in modelsim. Textio is not appropriate for synthesys, hence why you cannot compile in Quartus.

    The error you are getting is a type missmatch, you probably need to convert them using the to_signed(int, size) function.

    If you are unfamiliar with this, and textio, I suggest you read some VHDL tutorials, as these are very basic parts of VHDL.

    --- Quote End ---

    Did you mean I need to convert constant Ce that includes all the alphabet to signed? Thanks for your concern Tricky!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    These values appear to be constants declared elsewhere.

    I highly suggest you learn about VHDL before trying to use this code.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    These values appear to be constants declared elsewhere.

    I highly suggest you learn about VHDL before trying to use this code.

    --- Quote End ---

    Sorry Tricky, I have learn VHDL before this . Maybe I need to learn more as your suggestion. Btw, can I ask another question? I have convert the constant in MDCTTB_PKG file as shown below:

    -- quantization matrix used in testbench

    constant Q_MATRIX_USED : I_MATRIX_TYPE := Q_CANON10D;

    signal X_size : SIGNED(ROMDATA_W-1 downto 0);

    constant Ce : COEM_TYPE :=

    (

    (to_signed(AP,X_size),to_signed(AP,X_size),to_signed(AP,X_size),to_signed(AP,X_size)),

    (to_signed(BP,X_size),to_signed(CP,X_size),to_signed(CM,X_size),to_signed(BM,X_size)),

    (to_signed(AP,X_size),to_signed(AM,X_size),to_signed(AM,X_size),to_signed(AP,X_size)),

    (to_signed(CP,X_size),to_signed(BM,X_size),to_signed(BP,X_size),to_signed(CM,X_size))

    );

    When I run, an error said "no feasible entries for subprogram "to_signed"." Did I do the conversion in wrong way? Really appreciated any helps here.Thank you
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    X Size needs to be an integer.

    --- Quote End ---

    Thanks a lot Tricky! I fixed it and learn something new here..thank you very much :)