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Altera_Forum
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9 years ago

HPS DDR3 in Cyclone V

Hello, Suppose we have a properly designed PCB with a Cyclone V SOC and DDR3 (routed to the HPS pins). I know that the HPS part is be able to load properly without any FPGA logic programmed a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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I assume that your preloader has been loaded onto the SD Card/QSPI and you did not change/modify it. Thus, even if you recompile your design for the FPGA, as long as the preloader remains untouched, the HPS DDR3 calibration will still be successful

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That's correct.

So even if I program the FPGA with a new RBF - as long as I don't update the files on the SD card - the newer SDRAM parameters won't take effect ?

I.E: these SDRAM parameters aren't manifested in the RBF in any way ?