HPS Bridge to DDR address map

Hi,

I'm trying to access the PL DDR from the HPS through the HPS-to-FPGA Bridge. I have built a qsys system for the same where I have provided an address range of 0x0-0x0fffffff to the UNIPHY DDR controller which is an offset from the 0xC0000000(Bridge address). I wanted to know the AXI to DDR address map. Say if my offset is 0xF0, what address on the DDR does it correspond to? Is there any document available for this? Please advice on this.

Thanks and Regards,

Nitin.