Honored ContributorHello i used the megawizard to instantiate a DCFIFO but it seems i can't write anything to the fifo.. my usedw never changes
Anyone has a verilog example of a code that is working??? I tried to let wrreq always at 1 and wrclck changes when i need to write something
Honored ContributorThere is something in the about wrreq being active and the dcfifo coming out of reset. If I see your .stp wrreq is high before the wr and rd clocks start. I couldn't find that you actually reset the dcfifo. I tried to compile your code in order to simulate it (using Quartus II 9.1SP2) but the snippet is not complete.
Honored ContributorHum i dont reset the fifo, i am only reseting the signals in my FIFOWRAPPER (signals that go inside the fifo)
Do i need to reset the fifo? How does the signals need to be in order to write in the FIFO? Is there a protocol that WRREQ and WRCLK must follow? Can't i just let wrreq at 1 and use a 50mhz clk to write?Honored ContributorBy the way Josyb or Kaz, any of you have msn or gtalk? it would be easier to talk in a "chat" way.. i really need this working :S
my google contact is andreprado88 at gmail dot com (you can e-mail me also).. thanksHonored ContributorHi,
dc fifo is straightforward and doesn't need any particular sequences. reset is not done by many people. I note that you connect to usedw two signals (write and read word counts). This should result in eror or warning at compilation(double drive). You should not do thatHonored Contributoroopp sorry. read count is commented out.
I am pretty sure you are either connecting something wrong or reading the wrong signalHonored ContributorYou are right Kaz, i was connecting the wrclk signal wrong in my wrapper ( i was generating one that was customized to my needs and instead of using my signal i was using the rdclk). Two weeks of work because of that :@:@
Thanks a LOT for the help. At least now i am more familiarized with the FIFO
