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Altera_Forum
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14 years ago

How to use PLL In FPGA

Hai Friends,in my design i am using a 50Mhz clock from fpga. but i need a clock of 1 khZ or less. i want to know about how to use pll in fpga my device name :EP2S60F672C3 Thanks in adva...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

1 kHz is too low a frequency for a pll. You need to use counters to generate a 1kHz signal. If you need it as a clock inside your system, you can use the generated 1kHz signal as a clock enable.