Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to use global clock network (Stratix)
Hi,
in the "Stratix Device Handbook, Volume 1", page 2-74, it is said that "The global clock networks can also be driven by internal logic . . . ". That is exactly what I want to do, but i don't know, how. I have a "generated clock" from the masterclock, by deviding the masterclock by 2. (I know, that I shouldn't do that, and i know, that here are many threads in this forum that are handling this topic, so please concentrate on my main question ;) . . . ) This signal drives a lot of registers in my design. It is working quite well, but I know that it is not nice that this generated clock register has so many fan outs. What I want to do is to feed the output of my clock generating register into a global clock net and all registers that were fed by it now should be fed by this global clock. What I wanted to do is to use a ALTCLKCTRL megafunction, but it is not supported by my Stratix device. But because the device handbook says, that it is possible, I would like to know, how. Thanks, Maik13 Replies
Altera_ForumWell, it seemed, as if my problem was solved, but it isn't.
One thing I have to correct: it is not a clock signal that I am generating, but a clock enable signal (verified by looking into the RTL-Viewer of my design). So I thought I can be very clever and use "Auto Global Register Control Signals" as assignment name for my signal. After compiling my design again with this setting, I see no change at all. My generated signal still has a very high number of fan outs. I would have expected, that the fanouts of this signal would decrease dramatically because it only has to feed the global register control line. How can I verify that the changes I made in the assignment editor actually took place in the compiled design? And what can I do to force this assignment I made? Thank you, Maik- Altera_Forum
Ahhh,
thanks Jake! Now, I know what I can do with this button "Global Signal"! Maik - Altera_Forum
You can use the assignment editor to place a global assignment on the net. The assignment is under logic options -> Global Signal. You can then select Global Clock as the assignment value.
Jake
