How to use ddr2 sram high performance controller

That's a strange one, it looks like the span of the timer is expanding during generation. Typically this only happens when you hook up a master wider than a native slave. The Nios II data master is twice the width of the timer slave port so even though the timer takes up 16 bytes it's span will get promoted to 32 bytes which you can see in SOPC Builder. Try putting the PIO and CPU on the same clock domain as everything else in your system to avoid having clock crossing adapters dropped down into your system.

If that doesn't solve the problem try putting the memory at 0x0 and then place the peripherals far apart like 0x04000000, 0x04001000, 0x04002000

*edit: Which timer configuration are you using? Recently 64-bit support was added which causes the address span to double.