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Honored Contributor
Honored Contributorhow to use clk edges
I used to programe like this : use rising edge of clk to output one data,and then use falling edge to capture data at next step,because I think if the data is align at the rising edge of clk,i can ca...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- when I use dsp core in fpga,it requre the input clk align to the center of data at rising edge --- Quote End --- No. It's sufficient to keep the setup and hold times. In most cases, the design compiler can easily achieve it, when all registers are clocked at the same edge.
