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Altera_Forum
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15 years ago

how to use clk edges

I used to programe like this : use rising edge of clk to output one data,and then use falling edge to capture data at next step,because I think if the data is align at the rising edge of clk,i can ca...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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when I use dsp core in fpga,it requre the input clk align to the center of data at rising edge

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No. It's sufficient to keep the setup and hold times. In most cases, the design compiler can easily achieve it, when all registers are clocked at the same edge.