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Honored Contributor
Honored ContributorHow to use Avalon-MM Master BFM with Avalon-ST API Wrapper in VHDL test bench
Hi All I will need to use a Avalon-MM-Master-BFM for a VHDL test bench. The DUT will be in VHDL. As the bfm are written in System Verilog, there is a wrapper call Avalon-MM-maser BFM wit...
Altera_ForumHonored Contributor
Honored ContributorI noticed that the latest release of the Verification IP Suite supports VHDL, however, have not looked into it. This thread has a master/slave example using SystemVerilog
http://www.alteraforum.com/forum/showthread.php?t=32952&page=3 If you have Modelsim full-edition, you can use it directly to test your VHDL. If you only have Modelsim-ASE, perhaps it'll give you enough to get started ... Cheers, Dave
