Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to use Avalon-MM Master BFM with Avalon-ST API Wrapper in VHDL test bench
Hi All I will need to use a Avalon-MM-Master-BFM for a VHDL test bench. The DUT will be in VHDL. As the bfm are written in System Verilog, there is a wrapper call Avalon-MM-maser BFM wit...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Did you guys have any experience in using the wrapper in VHDL test bench? If you can share the experience, I would like to have an example in showing correct usage of it. --- Quote End --- The VHDL wrapper is pretty much useless. Its missing all the VHDL procedures needed to implement the API. If you have a mixed language simulator (Modelsim full-edition), then you can just use SystemVerilog to test your VHDL device. The other issue with using the Verification IP suite is that the checking logic uses System Verilog Assertions, so the bus monitors only work with a full version of Modelsim too. Cheers, Dave
