how to understand some note in an477

I guess you are referring to AN447?

The document's main concern is keeping safe input voltages for FPGAs. Driving a FPGA by 3.3V logic is a critical case from it's viewpoint. Using correct source side serial termination there's should be no problem. Previous FPGA families had "Multi-IO" voltage tables saying 3.3V can drive 1.5 to 3.3V CMOS on input.

The input overdriving aspect involves a rather asymmetrical threshold and a certain delay asymmetry. You should also care for a reliable low level. If delay symmetry is an objective, you can think about using voltage dividers as level translaters.