How to troubleshoot QSYS Error Messages

**** PROBLEM SOLVED -- SEE NOTE AT END ****

I've used QSYS a couple of times before with good success, but my custom components have all been Avalon Memory Mapped Slaves for serial a/d and d/a converters, i/o ports and other relatively simple stuff.

This time, I've created a simple Avalon Streaming Source packet generator that feeds into a Triple Speed Ethernet Core. I've added in a timing adapter, per QSYS's suggestion.

The new component seems to be generated properly and I can get QSYS to generate the system without error. When I go to compile the full FPGA, I get the following warning and error messages:

• Warning (12251): Tse.gen_avalon_0.avalon_streaming_source_0: gen_avalon_0.avalon_streaming_source_0 must be connected to an Avalon-ST sink

• Warning (12251): Tse.gen_avalon_0: gen_avalon_0.conduit_end_1 must be exported, or connected to a matching conduit.

• Warning (12251): System: "No matching role found for timing_adapter:in:in_endofpacket (endofpacket)"

• Warning (12251): System: "No matching role found for timing_adapter:in:in_valid (valid)"

• Warning (12251): System: "No matching role found for timing_adapter:in:in_startofpacket (startofpacket)"

• Warning (12251): System: "No matching role found for timing_adapter:in:in_error (error)"

• Warning (12251): System: "No matching role found for timing_adapter:in:in_empty (empty)"

• Warning (12251): System: "No matching role found for timing_adapter:in:in_data (data)"

• Warning (12251): System: "No matching role found for timing_adapter:in:in_ready (ready)"

• Error (12252): Tse.gen_avalon_0.gen_avalon/timing_adapter.in: An Avalon Streaming connection can only connect an Avalon Streaming Source to an Avalon Streaming Sink

• Error (12252): Tse.gen_avalon_0.gen_avalon/timing_adapter.in: Missing connection start (try "Remove Dangling Connections")

• Error (12252): Error writing sopcinfo report java.lang.NullPointerException

• Error (12252): Error writing html report java.lang.NullPointerException

• Error (12153): Can't elaborate top-level user hierarchy

I've looked at the signals and they all seem to be connected properly, and the signal direction seems to match what I'd like. I'm using Quartus 12.0.

**** SOLUTION ****

The custom component had been originally located outside of the QSYS system directory tree. Although the component could be included into the QSYS project and would be compiled correctly, the component wouldn't show up if I went to edit the QSYS project. I moved the module to be under the QSYS project. This appeared to work, as the QSYS project could be regenerated without errors.

However, when I compiled the whole project, the Quartus compiler couldn't find this component and gave me errors. I ended up deleting the QSYS project and creating it from scratch using the component located underneath the same directory tree, and this worked. Evidently, the component directory path must not be correctly updated in some configuration file; it looks fine inside the project files window, though.

Thanks to anyone who took the time to read this.