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2258432's avatar
2258432
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

How to transmit video data to DDR and display ?

Hi all, I have used the test pattern generator II IP in Platform Designer to generate video data and connected its dout to the din of the clocked video output II IP. Finally, I output the video to H...
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Programmable Logic Device
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Lii Yuhang,


Good day.

May I know do you have 2 FPGA in 1 board?

It seems like you have 2 boards, is this correct?


You may setup your connection as below if you have 2 boards connected with ethernet.


Board 1: TPG-->frame buffer (write only mode) -->MSGDMA(read only)-->ethernet


Board 2: ethernet--> MSGDMA(write only to DDR3)-->frame buffer (read only mode)-->CVO-->HDMI display


Hope this answers your question.

Thank you.

Best Regards,

ZH_Intel



  • 2258432's avatar
    2258432
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hello ZH_Intel,

    Thanks for your guidance.


    You are right, I have two Cyclone V boards.


    I will first review the official documentation to learn how to use VFB's writer control and reader control, and then follow your guidance to try it out.


    Thank you again, please close this thread.

    Best regards.

    • ZH_Intel's avatar
      ZH_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      1 year ago

      Hi Lii Yuhang,

      Good day.

      Thank you for your reply.

      I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

      Thank you.

      Best Regards,

      ZH_Intel