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2258432's avatar
2258432
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

How to transmit video data to DDR and display ?

Hi all, I have used the test pattern generator II IP in Platform Designer to generate video data and connected its dout to the din of the clocked video output II IP. Finally, I output the video to H...
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Programmable Logic Device
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi there,


Good day.

We would like to suggest you to use the frame buffer instead of MGDMA.

Frame buffer is for moving video from/to DDR.

You may setup your connection as below:

Test Pattern Generator (TPG)-->Frame buffer---> CVO (Clock Video Output)-->HDMI TX.


You may refer to below document. In this document states what is the function of frame buffer, types of connection, parameter settings, application examples and more:

https://www.intel.com/content/www/us/en/docs/programmable/683416/22-1/about-the-video-and-image-processing-suite.html


Hope this answers your question.

Thank you.

Best Regards,

ZH_Intel


  • 2258432's avatar
    2258432
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hello ZH_Intel,

    Thanks for your assistance.

    Following your instructions, I've successfully used the frame buffer, and now the video is displaying properly. Additionally, I've used memtool in Linux to check DDR3, and confirmed that the frame buffer is writing data into DDR3.

    My purpose is to send this video data to a second Cyclone V SoC and display the video there. My initial plan was to use MSGDMA to transfer the video data generated by TPG to DDR3 first, and then send this data through Ethernet in Linux. The second SoC would then receive the video data and display it.

    If I'm using the frame buffer, how can I send the video data out?

    thanks again for your assistance.

    Best regards.