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RLedu's avatar
RLedu
Icon for New Contributor rankNew Contributor
3 years ago

How to test HPS-FPGA project with time limited sof

Hello dear community, I am currently working on a project using a licensed IP (JESD204B) controlled through HPS that I didn't buy yet, but I do have the evaluation IP. This leads to get a time li...
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi RLedu,


The Linux will freeze and required a re-boot if your system is accessing the design content in the FPGA during runtime while you are trying to reprogram the content in FPGA.

You can avoid that by making sure that your system is not accessing the FPGA when you are trying to re-program it during runtime.

Due to the time limit for the evaluation IP which leads to your problem, I suggest you can try contact the sale personal about your issue to further query any other options that might work for your case.


Thanks.

Regards,

Aik Eu