How to test HPS-FPGA project with time limited sof

Hi aikeu,

Thank you for your answer, in deed let me clarify.

I want to program my FPGA (5CSXFC6D6F31C6N) with a ".sof" compiled verilog project. This project includes HPS IP from qsys and other FPGA IPs, in particular a JESD204B IP which requires a license.

This means that my .sof project is time limited because I only have an evaluation license of the JESD204B IP.

So the only way to program the FPGA is through the programmer and usb blaster connexion, I cannot convert .sof into .rbf since time limited won't allow it.

This is problematic since in this post link it is mentionned that you cannot at the same time program FPGA with .sof and expect the linux to keep running, or at least it is not guaranteed.

In my case, freezing means I don't have any control over the Linux through putty for instance (serial or ssh).

So I wonder if there is a proper way to program FPGA through the programmer and to ensure the OS functionning without rebooting ?

Regards,