How to support four DDR3 ports running at 800MHz using Stratix5?

I have a hardware project needs FPGA solution which can take two x8 PCIe Gen2 interfaces on one side and support 4 DDR3 800MHz SODIMM ports on the other side. My main question is how to ensure that four DDR3 800MHz ports work fully.

In the past we designed similar hardware using Stratx4GX 530 board which supported two Gen2 x 8 interfaces and four DDR3 533 SODIMM interfaces. For the most part it worked but we kept seeing random single bit failures. We had to raise the voltage to control the issue.

So this time around, I am not sure how to resolve it from the beginning and design it right. I would like to know how to architect the DDR3 interfaces. Do you think that having the design split into multilple FPGAs is required to acheive this? I would like to avoid splitting the design into multiple FPGAs due to mechanical constraint and cost.

Your feeback will be great.

Thanks.