Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

how to speed up the read-modify-write DDR2 with HPC II?

Want to implement "read -modify -write" to ddr2 on DE4 Board( stratix iv gx + ddr2

so dimm),but when i read the ddr2,the data will appear after decades periods,

and then modify & write back. the speed is lowest.

how to speed it up ? or can't.

any help will be appreciated.!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Use burst operation.Read 8,16 or more words from ddr to on-chip ram one time, then modify one by one, last wirte back to ddr.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    For single word transfers you may have to live with the delays.

    DDR2 is fast for burst accesses transfers, but the 'time to first data' for memory reads hasn't really changed much over the last 20 years.

    A 3.5GHz x86 cpu will only run at anything like that speed when all the code and data is cached.

    If you are doing occaisional random accesses, then you might find that an uncached read will return data sooner than a read via the data cache.

    But then you need to be very careful about interactions with any data caches.

    FWIW I see 16 clocks for isolated random uncached reads of SDRAM. DDR and DDR2 are very unlikely to be faster - and may be slower.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    thanks for your post.

    I know the burst access for ddr/2. I wonder the pure random access with ddr2.

    the probablity to speed up the ddr2 random access: such as , just random access

    the same bank or row/col, or phy only, or something.

    thanks again!

    --- Quote Start ---

    For single word transfers you may have to live with the delays.

    DDR2 is fast for burst accesses transfers, but the 'time to first data' for memory reads hasn't really changed much over the last 20 years.

    A 3.5GHz x86 cpu will only run at anything like that speed when all the code and data is cached.

    If you are doing occaisional random accesses, then you might find that an uncached read will return data sooner than a read via the data cache.

    But then you need to be very careful about interactions with any data caches.

    FWIW I see 16 clocks for isolated random uncached reads of SDRAM. DDR and DDR2 are very unlikely to be faster - and may be slower.

    --- Quote End ---