How to solve the error: "register does not hold its value outside the clock edge

Hi,

I'm a beginner in VHDL. I encounter this error when trying to complile my vhdl. Below is my vhdl code that cause the error:

DataHoldRegister_temp_process3 : PROCESS (clk, reset)

BEGIN

IF reset = '1' THEN

regout <= (OTHERS => '0');

ELSIF clk'event AND clk = '1' THEN

IF enb_128_128_1 = '1' THEN

regout <= muxout;

END IF;

END IF;

END PROCESS DataHoldRegister_temp_process3;

Upsample_out1 <= muxout WHEN ( enb_128_128_1 = '1' ) ELSE

regout;

s_1 <= std_logic_vector(Upsample_out1);

s_2 <= signed(Digital_Filter1_out1);

Gain3_gainparam <= '1';

test_gain3: process(Compare_To_Zero_out1) is

begin

if Compare_To_Zero_out1 = '1' then

Gain3_out1 <= "010000000000000000";

elsif Compare_To_Zero_out1 = '0' then

Gain3_out1 <= "110000000000000000";

end if;

end process test_gain3;

sub_cast <= resize(s_2, 18);

sub_cast_1 <= Gain3_out1;

sub_temp <= resize(sub_cast, 19) - resize(sub_cast_1, 19);

Sum_out1 <= sub_temp(17 DOWNTO 0);

s_3 <= std_logic_vector(Sum_out1);

s_4 <= signed(Integrator2_out1);

Gain_gainparam <= '1';

test_gain: process(Compare_To_Zero_out1) is

begin

if compare_to_zero_out1 = '1' then

gain_out1 <= "00101001011100001010";

elsif compare_to_zero_out1 = '0' then

gain_out1 <= "11010110100011110110";

end if;

end process test_gain;

The error:

Error (10818): Can't infer register for "Gain_out1[0]" at sub.vhd(244) because it does not hold its value outside the clock edge.

Any suggestions to solve the problem?