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Honored Contributor
Honored ContributorHow to simulate the FPGA neural network in Altera
I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simul...
Altera_ForumHonored Contributor
Honored ContributorOK you seem to not understand the fundamentals of FPGAs.
HDL is a hardware - description language. It isn't software. Hardware needs a defined input and an output. Right now it simulink your "inputs" are some constants, but when you convert to HDL using HDLCoder you basically have a system without any "input ports" and "output ports". This means that when the synthesizer looks at your design it sees it doing nothing. Since the digital design works (sinmulink44_dig2009a.mdl) you need to replace your constant inputs with input ports (look in the simulink library) and replace the output scope you have with an output port. Set their data types to fixdt(1,12,6). Then regenerate the HDL. It should recognize several 12 - bit inputs (input1, input2, input3....) and one 12 - bit output. Then you can send this to Modelsim and look at each 12 -bit bus. If you need more explanation about fixed point representation just search "matlab fixed point toolbox" on google. There are plenty examples and explanations. Altera's DSP blockset also needs fixed point toolbox.
